K4H281638L Datasheet, PDF (11/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification

K4H281638L
DDR SDRAM
7.2 Mode Register Definition
Mode Register Set(MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing
mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli-
cations. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper
DDR SDRAM operation. The mode register is written by asserting low on CS, RAS, CAS, WE and BA0(The DDR SDRAM should be in
all bank precharge with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A11 in the same cycle
as CS, RAS, CAS, WE and BA0 going low are written in the mode register. Two clock cycles are requested to complete the write opera-
tion in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst
length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test
mode. A8 is used for DLL reset. A7 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst
lengths, addressing modes and CAS latencies.
BA1 BA0 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
RFU 0
RFU
DLL TM
CAS Latency
BT
Burst Length
Address Bus
Mode Register
A8 DLL Reset
0
No
1
Yes
A7
mode
0
Normal
1
Test
A3 Burst Type
0
Sequential
1
Interleave
BA0
An ~ A0
0 (Existing)MRS Cycle
1 Extended Funtions(EMRS)
* RFU(Reserved for future use)
must stay "0" during MRS cycle.
CAS Latency
A6 A5 A4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Latency
Reserve
Reserve
Reserve
3
Reserve
Reserve
2.5
Reserve
Burst Length
A2 A1 A0
000
001
010
011
100
101
110
111
Burst Length
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Note : *1 A12 is used for 256Mb only. That is 128Mb uses A0~A11
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Rev. 1.2 Feburary 2009