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K4H281638L Datasheet, PDF (16/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification
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K4H281638L
DDR SDRAM
2M x 16Bit x 4 Banks Double Data Rate SDRAM
10.0 General Description
The K4H281638L is 134,217,728 bits of double data rate synchronous DRAM organized as 4x 2,097,152 words by 16bits, fabricated
with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to
500Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and
programmable latencies allow the device to be useful for a variety of high performance memory system applications.
11.0 Absolute Maximum Rating
Parameter
Symbol
Value
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
Voltage on VDD & VDDQ supply relative to VSS
VDD, VDDQ
1.0 ~ 3.6
Storage temperature
TSTG
-55 ~ +150
Power dissipation
PD
1
Short circuit current
IOS
50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Unit
V
V
°C
W
mA
12.0 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage (for device with a nominal VDD of 2.5V for DDR333, 400)
VDD
2.3
2.7
V
Supply voltage (for device with a nominal VDD of 2.5V for DDR500)
VDD
2.375
2.625
V
I/O Supply voltage (for device with a nominal VDD of 2.5V for DDR333, 400) VDDQ
2.3
2.7
V
I/O Supply voltage (for device with a nominal VDD of 2.5V for DDR500)
VDDQ
2.375
2.625
V
I/O Reference voltage
VREF
0.49*VDDQ 0.51*VDDQ
V
1
I/O Termination voltage(system)
VTT
VREF-0.04 VREF+0.04
V
2
Input logic high voltage
VIH(DC) VREF+0.15 VDDQ+0.3
V
Input logic low voltage
VIL(DC)
-0.3
VREF-0.15
V
Input Voltage Level, CK and CK inputs
VIN(DC)
-0.3
VDDQ+0.3
V
Input Differential Voltage, CK and CK inputs
VID(DC)
0.36
VDDQ+0.6
V
3
V-I Matching: Pullup to Pulldown Current Ratio
VI(Ratio)
0.71
1.4
-
4
Input leakage current
II
-2
2
uA
Output leakage current
IOZ
-5
5
uA
Output High Current(Full strengh driver) ; VOUT=VDDQ-0.388V
IOH
-13.8
-16.1
mA
Output LowCurrent(Full strengh driver) ; VOUT=0.388V
IOL
16.5
19.2
mA
Output High Current(Week strengh driver) ; VOUT=VDDQ-0.538V
IOH
-18.2
-21.8
mA
Output Low Current(Week strengh driver) ; VOUT=0.538V
IOL
20.2
24.5
mA
Output High Current(Mached strengh driver) ; VOUT=VDDQ-0.6505V
IOH
-15.5
-18.9
mA
Output Low Current(Mached strengh driver) ; VOUT=0.6505V
IOL
17
21.3
mA
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari-
ations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
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Rev. 1.2 Feburary 2009
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