K4H281638L Datasheet, PDF(10/32 Page) Samsung semiconductor

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K4H281638L Datasheet, PDF (10/32 Pages) Samsung semiconductor – 128Mb L-die DDR SDRAM Specification

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K4H281638L

DDR SDRAM

7.0 FUNCTIONAL DESCRIPTION

7.1 Power-up & Initialization Sequence

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may

result in undefined operation. No power sequencing is specified during power up and power down given the following

â¢ VDD and VDDQ are driven from a single power converter output, AND

â¢ VTT is limited to 1.35 V, AND

â¢ VREF tracks VDDQ/2 OR, the following relationships must be followed:

â¢ VDDQ is driven after or with VDD such that

â¢ VDDQ < VDD + 0.3 V AND

â¢ VTT is driven after or with VDDQ such that VTT < VDDQ + 0.3 V, AND

â¢ VREF is driven after or with VDDQ such that VREF < VDDQ + 0.3 V.

At least one of these two conditions must be met.

Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power up is required to guarantee that the DQ and DQS

outputs will be in the HighâZ state, where they will remain until driven in normal operation (by a read access). After all power supply and

reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200 Âµs delay prior to applying an executable com-

mand. Once the 200 Âµs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought

HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a MODE REGISTER SET command

should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the

Mode Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and

any read command. A PRECHARGE ALL command should be applied, placing the device in the âall banks idleâ state.

Once in the idle state, two AUTO refresh cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Reg-

ister, with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) must be performed. Following

these cycles, the DDR SDRAM is ready for normal operation.

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Rev. 1.2 Feburary 2009

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