K4T56043QF Datasheet, PDF (3/27 Pages) Samsung semiconductor – 256Mb F-die DDR2 SDRAM

256Mb F-die DDR2 SDRAM
0. Ordering Information
Organization
DDR2-667 5-5-5
64Mx4
-
64Mx4
-
32Mx8
K4T56083QF-GCE6
32Mx8
K4T56083QF-ZCE6
Note: Speed bin is in order of CL-tRCD-tRP
DDR2-533 4-4-4
K4T56043QF-GCD5
K4T56043QF-ZCD5
K4T56083QF-GCD5
K4T56083QF-ZCD5
DDR2-400 3-3-3
K4T56043QF-GCCC
K4T56043QF-ZCCC
K4T56083QF-GCCC
K4T56083QF-ZCCC
1.Key Features
DDR2 SDRAM
Package
Leaded
Lead-free
Leaded
Lead-free
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-667
5-5-5
5
15
15
54
DDR2-533
4-4-4
4
15
15
55
DDR2-400
3-3-3
3
15
15
55
Units
tCK
ns
ns
ns
• JEDEC standard 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 200 MHz f_CK for 400Mb/sec/pin, 267MHz f_CK for
533Mb/sec/pin, 333MHz f_CK for 667Mb/sec/pin
• 4 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Average Refesh Period 7.8us at lower then T_CASE 85°C,
3.9us at 85°C < T_CASE < 95 °C
The 256Mb DDR2 SDRAM chip is organized as either
16Mbit x 4 I/Os x 4 banks or 8Mbit x 8 I/Os x 4banks
device. This synchronous device achieves high speed dou-
ble-data-rate transfer rates of up to 667Mb/sec/pin (DDR2-
667) for general applications.
The chip is designed to comply with the following key
DDR2 SDRAM features such as posted CAS with additive
latency, write latency = read latency - 1, Off-Chip
Driver(OCD) impedance adjustment and On Die Termina-
tion.
All of the control and address inputs are synchronized with
a pair of externally supplied differential clocks. Inputs are
latched at the crosspoint of differential clocks (CK rising
and CK falling). All I/Os are synchronized with a pair of
bidirectional strobes (DQS and DQS) in a source synchro-
nous fashion. The address bus is used to convey row, col-
umn, and bank address information in a RAS/CAS
multiplexing style. For example, 256Mb(x4) device receive
13/11/2 addressing.
The 256Mb DDR2 device operates with a single
1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 256Mb DDR2 device is available in 60ball
FBGAs(x4/x8).
• Package: 60ball FBGA - 64Mx4/32Mx8
• All of Lead-free products are compliant for RoHS
Note: The functionality described and the timing specifica-
tions included in this data sheet are for the DLL Enabled
mode of operation.
Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features
which are described in “Samsung’s DDR2 SDRAM Device Operation & Timing Diagram”
Page 3 of 27
Rev. 1.5 Feb. 2005