K4T56043QF Datasheet, PDF (26/27 Pages) Samsung semiconductor – 256Mb F-die DDR2 SDRAM

256Mb F-die DDR2 SDRAM
DDR2 SDRAM
31. Input waveform timing is referenced from the input signal crossing at the V_IH(ac) level for a rising signal and V_IL(ac)
for a falling signal applied to the device under test.
32. Input waveform timing is referenced from the input signal crossing at the V_IH(dc) level for a rising signal and V_IL(dc)
for a falling signal applied to the device under test.
CK
CK
tIS tIH
tIS tIH
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF(dc)
V_IL(dc) max
V_IL(ac) max
V_SS
33. tWTR is at lease two clocks (2 * tCK) independent of operation frequency.
34. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input
signal crossing at the VIH(ac) level to the single-ended data strobe crossing VIH/L(dc) at the start of its tran-
sition for a rising signal, and from the input signal crossing at the VIL(ac) level to the single-ended data strobe
crossing VIH/L(dc) at the start of its transition for a falling signal applied to the device under test. The DQS
signal must be monotonic between Vil(dc)max and Vih(dc)min.
35. Input waveform timing with single-ended data strobe enabled MR[bit10] = 1, is referenced from the input
signal crossing at the VIH(dc) level to the single-ended data strobe crossing VIH/L(ac) at the end of its transi-
tion for a rising signal, and from the input signal crossing at the VIL(dc) level to the single-ended data strobe
crossing VIH/L(ac) at the end of its transition for a falling signal applied to the device under test. The DQS
signal must be monotonic between Vil(dc)max and Vih(dc)min.
36. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE
must remain at the valid input level the entire time it takes to achieve the 3 clocks of registeration. Thus, after
any cKE transition, CKE may not transitioin from its valid level during the time period of tIS + 2*tCK + tIH.
Page 26 of 27
Rev. 1.5 Feb. 2005