K4T56043QF Datasheet, PDF (17/27 Pages) Samsung semiconductor – 256Mb F-die DDR2 SDRAM

256Mb F-die DDR2 SDRAM
DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
Parameter
Symbol
DQ output access time tAC
from CK/CK
DQS output access
time from CK/CK
tDQSCK
CK high-level width
tCH
CK low-level width
tCL
CK half period
tHP
Clock cycle time, CL=x tCK
DQ and DM input hold
time
tDH(base)
DQ and DM input
setup time
tDS(base)
Control & Address
input pulse width for
each input
tIPW
DQ and DM input
pulse width for each
input
tDIPW
Data-out high-
tHZ
impedance time from
CK/CK
DQS low-impedance
time from CK/CK
tLZ(DQS)
DQ low-impedance
time from CK/CK
tLZ(DQ)
DQS-DQ skew for
DQS and associated
DQ signals
tDQSQ
DQ hold skew factor
tQHS
DQ/DQS output hold
tQH
time from DQS
First DQS latching
transition to associated
clock edge
tDQSS
DQS input high pulse
width
tDQSH
DQS input low pulse
width
tDQSL
DQS falling edge to
CK setup time
tDSS
DQS falling edge hold
time from CK
tDSH
DDR2-667
min
max
-450
+450
DDR2-533
min max
-500
+500
DDR2-400
min
max
-600
+600
-400
+400
-450
+450
-500
+500
0.45
0.45
min(tCL
, tCH)
3000
175
0.55
0.55
x
8000
x
0.45
0.45
min(tCL
, tCH)
3750
225
0.55
0.55
x
8000
x
0.45
0.45
min(tCL
, tCH)
5000
275
0.55
0.55
x
8000
x
100
x
100
x
150
x
0.6
x
0.6
x
0.6
x
0.35
x
0.35
x
0.35
x
x
tAC
x
tAC
x
tAC
max
max
max
tAC
tAC
tAC
tAC
tAC
tAC
min
max
min
max
min
max
2*tAC
tAC
2* tAC
tAC
2* tAC
tAC
min
max
min
max
min
max
x
240
x
300
x
350
x
340
x
400
x
450
tHP -
x
tHP -
x
tHP -
x
tQHS
tQHS
tQHS
-0.25
0.25
-0.25
0.25
-0.25
0.25
0.35
x
0.35
x
0.35
x
0.35
x
0.35
x
0.35
x
0.2
x
0.2
x
0.2
x
0.2
x
0.2
x
0.2
x
Page 17 of 27
Units Notes
ps
ps
tCK
tCK
ps
20,21
ps
24
ps
15,16,
17,20
ps
15,16,
17,21
tCK
tCK
ps
ps
27
ps
27
ps
22
ps
21
ps
tCK
tCK
tCK
tCK
tCK
Rev. 1.5 Feb. 2005