K4T51043QG Datasheet, PDF (22/47 Pages) Samsung semiconductor – 512Mb G-die DDR2 SDRAM Specification

K4T51043QG
K4T51083QG
K4T51163QG
DDR2 SDRAM
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)
(For information related to the entries in this table, refer to both the general notes and the specific notes following this table.)
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK HIGH pulse width
CK LOW pulse width
Symbol
tAC
tDQSCK
tCH
tCL
DDR2-533
min
max
-500
500
-450
450
0.45
0.55
0.45
0.55
DDR2-400
min
max
-600
600
-500
500
0.45
0.55
0.45
0.55
Units
ps
ps
tCK
tCK
Notes
CK half pulse period
Clock cycle time, CL=x
DQ and DM input hold time (differential strobe)
tHP
tCK
tDH(base)
Min(tCL, tCH)
3750
225
x
8000
x
Min(tCL, tCH)
5000
275
x
8000
x
ps
11,12
ps
15
ps
6,7,8,21,28
DQ and DM input setup time (differential strobe)
DQ and DM input hold time (single-ended strobe)
DQ and DM input setup time (single-ended strobe)
tDS(base)
100
tDH1(base)
-25
tDS1(base)
-25
x
150
x
25
x
25
x
ps
6,7,8,20,28
x
ps
6,7,8,26
x
ps
6,7,8,25
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
tIPW
tDIPW
tHZ
0.6
x
0.6
x
tCK
0.35
x
0.35
x
tCK
x
tAC(max)
x14
tAC(max)
ps
18
DQS(/DQS) low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
tLZ(DQS)
tAC(min) tAC(max)
tAC(min)
tAC(max)
ps
18
tLZ(DQ)
2* tAC(min) tAC(max) 2* tAC(min) tAC(max)
ps
18
tDQSQ
x
300
x
350
ps
13
DQ hold skew factor
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
DQS input LOW pulse width
tQHS
tQH
tDQSS
tDQSH
tDQSL
x
400
x
450
ps
12
tHP - tQHS
x
tHP - tQHS
x
ps
-0.25
0.25
-0.25
0.25
tCK
0.35
x
0.35
x
tCK
0.35
x
0.35
x
tCK
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
tDSS
tDSH
tMRD
0.2
x
0.2
x
tCK
0.2
x
0.2
x
tCK
2
x
2
x
tCK
MRS command to ODT update delay
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
tMOD
tWPST
tWPRE
tIH(base)
tIS(base)
0
12
0.4
0.6
0.35
x
375
x
250
x
0
0.4
0.35
475
350
12
ns
0.6
tCK
10
x
tCK
x
ps
5,7,9,23
x
ps
5,7,9,22
Read preamble
Read postamble
Active to active command period for 1KB page size products
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
tCK
19
0.4
0.6
0.4
0.6
tCK
19
7.5
x
7.5
x
ns
4
Active to active command period for 2KB page size products tRRD
10
x
10
x
ns
4
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Rev. 1.4 December 2008