K4T51043QG Datasheet, PDF (20/47 Pages) Samsung semiconductor – 512Mb G-die DDR2 SDRAM Specification

K4T51043QG
K4T51083QG
K4T51163QG
DDR2 SDRAM
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)
(For information related to the entries in this table, refer to both the general notes and the specific notes following this table.)
Parameter
Symbol
DDR2-800
min
max
DDR2-667
min
max
Units
Notes
DQ output access time from CK/CK
DQS output access time from CK/CK
tAC
tDQSCK
-400
400
-450
450
ps
40
-350
350
-400
400
ps
40
Average clock HIGH pulse width
Average clock LOW pulse width
CK half pulse period
tCH(avg)
tCL(avg)
tHP
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
Min(tCL(abs),
tCH(abs))
x
Min(tCL(abs),
tCH(abs))
x
tCK(avg)
tCK(avg)
ps
35,36
35,36
37
Average clock period
DQ and DM input hold time
DQ and DM input setup time
tCK(avg)
tDH(base)
tDS(base)
2500
125
50
8000
x
x
3000
175
100
8000
x
x
ps
35,36
ps
6,7,8,21,28,31
ps
6,7,8,20,28,31
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
tIPW
tDIPW
tHZ
0.6
x
0.6
x
tCK(avg)
0.35
x
0.35
x
tCK(avg)
x
tAC(max)
x
tAC(max)
ps
18,40
DQS/DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
tLZ(DQS)
tLZ(DQ)
tDQSQ
tAC(min)
tAC(max)
tAC(min) tAC(max)
ps
2* tAC(min) tAC(max) 2* tAC(min) tAC(max)
ps
x
200
x
240
ps
18,40
18,40
13
DQ hold skew factor
DQ/DQS output hold time from DQS
DQS latching rising transitions to associated clock edges
DQS input HIGH pulse width
DQS input LOW pulse width
tQHS
tQH
tDQSS
tDQSH
tDQSL
x
300
x
340
ps
38
tHP - tQHS
x
tHP - tQHS
x
ps
39
- 0.25
0.25
-0.25
0.25
tCK(avg)
30
0.35
x
0.35
x
tCK(avg)
0.35
x
0.35
x
tCK(avg)
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
tDSS
tDSH
tMRD
0.2
x
0.2
x
tCK(avg)
30
0.2
x
0.2
x
tCK(avg)
30
2
x
2
x
nCK
MRS command to ODT update delay
Write postamble
Write preamble
tMOD
tWPST
tWPRE
0
12
0.4
0.6
0.35
x
0
0.4
0.35
12
ns
32
0.6
tCK(avg)
10
x
tCK(avg)
Address and control input hold time
tIH(base)
Address and control input setup time
tIS(base)
Read preamble
tRPRE
Read postamble
tRPST
Activate to activate command period for 1KB page size products tRRD
250
x
275
x
ps
5,7,9,23,29
175
x
200
x
ps
5,7,9,22,29
0.9
1.1
0.9
1.1
tCK(avg)
19,41
0.4
0.6
0.4
0.6
tCK(avg)
19,42
7.5
x
7.5
x
ns
4,32
Activate to activate command period for 2KB page size products tRRD
10
x
10
x
ns
4,32
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Rev. 1.4 December 2008