BU7331EKN-E2 Datasheet, PDF (1/21 Pages) Rohm – 3ch Programmable Clock Generator

3ch Programmable Clock Generator
Generate
3 application clocks
BU7331EKN
No.09004EAT01
●Description
The BU7331EKN integrates a 3ch PLL.The frequency of each PLL can be set via serial interface control, making it
compatible with a wide range of digital applications.
In addition, sudden frequency changes are handled via rewriting through the register, and BU7331EKN is suitable for sets
with different frequencies, resulting in more efficient parts management and shorter development time.
●Features
1) To generate clocks by connecting reference 5.0MHz ～ 48.0MHz.
2) 5.0MHz～75.0MHz output frequency range.
3) All settings and operation controlled via 2-wire serial interface
4) Individual level shifter attached to each output
5) HQFN20V package
●Application
General digital product of mobile phone, DSC, DVD-player etc.
●Absolute Maximum ratings (Ta=25℃)
Parameter
Symbol
Supply voltage (Core)
VDD_CORE
Supply voltage (I/O)
VDD_IO
Input Voltage
VIN
Storage Temperature range
Tstg
Power dissipation
PD
*¹ A measure value at mounting on 70 x 70 x 1.6mm glass epoxy substrate.
In the case of exceeding Ta=25℃, 6.0mW should be reduced per 1℃.
* The radiation-resistance design is not carried out.
* Operation is not guaranteed.
Limits
Unit
-0.2 ~ 2.2
V
-0.2 ~ 4.0
V
-0.2 ~ VDD+0.2
V
-55 ~ 125
℃
599.8 *¹
mW
●Operating Conditions
Parameter
Symbol
Limits
Supply voltage (Core)
VDD_CORE
1.65 ~ 1.80 ~ 1.95
Supply voltage (VDD_CLK)
Supply voltage (VDD_SIF)
VDD_CLK
VDD_SIF
1.40 ~ 3.60
1.40 ~ 3.60 *¹
Input ”H” Voltage
VIH
0.8VDD ~ VDD
Input ”L” Voltage
VIL
0.0 ~ 0.2VDD
Operating Temperature
Input frequency ( xtal use ) *²
Input frequency ( Not xtal use ) *³
topr
Ref_xtal
Ref_clk
-20 ~ 75
5.0 ~ 27.0
5.0 ~ 48.0
5~48MHz Output Load1 (VDD_CLK=1.40~1.65V)
CL1
10 (MAX)
5~48MHz Output Load 2 (VDD_CLK=1.65~3.60V)
CL2
15 (MAX)
5~75MHz Output Load (VDD_CLK=2.70~3.60V)
CL3
15 (MAX)
*1 When setting it as VDD_SIF=1.40V～1.45V, standby current may flow by VDD_CORE=1.90V～1.95V.
Use by VDD_CORE=1.80V is recommended.
*2 Need a resister for bias between 6PIN and 7PIN.
*3 The input amplitude level range is 0.6Vp-p ～ VDD_COREp-p.
Refer to application note about input form details.
Unit
V
V
V
V
V
℃
MHz
MHz
pF
pF
pF
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2009.04 - Rev.A