H8S-2639 Datasheet, PDF (941/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 21C ROM (H8S/2635 Group)
21C.7.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically
cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory erase block configuration is shown in table 21C-7.
Bit: 7
6
5
4
3
2
1
0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
21C.7.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even
though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2
combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and
EBR2 to be automatically cleared to 0. On the H8S/2635 bits 7 to 3 are reserved. Only 0 may be
written to these reserved bits. When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
The flash memory erase block configuration is shown in table 21C-7.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
EB10 EB9 EB8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Note: Bits 7 to 3 are reserved and only 0 may be written to them.
Rev. 6.00 Feb 22, 2005 page 881 of 1484
REJ09B0103-0600