H8S-2639 Datasheet, PDF (119/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 2 CPU
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * Not available in the chip.
Figure 2-13 Branch Address Specification in Memory Indirect Mode
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address (For further information, see section 2.5.2, Memory
Data Formats).
2.7.2 Effective Address Calculation
Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal
mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: * Not available in the chip.
Rev. 6.00 Feb 22, 2005 page 59 of 1484
REJ09B0103-0600