H8S-2639 Datasheet, PDF (44/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

10.2.6 Timer Counter (TCNT)........................................................................................ 332
10.2.7 Timer General Register (TGR) ............................................................................ 333
10.2.8 Timer Start Register (TSTR) ............................................................................... 334
10.2.9 Timer Synchro Register (TSYR) ......................................................................... 335
10.2.10 Module Stop Control Register A (MSTPCRA) ................................................... 336
10.3 Interface to Bus Master..................................................................................................... 337
10.3.1 16-Bit Registers ................................................................................................... 337
10.3.2 8-Bit Registers ..................................................................................................... 337
10.4 Operation .......................................................................................................................... 339
10.4.1 Overview.............................................................................................................. 339
10.4.2 Basic Functions.................................................................................................... 340
10.4.3 Synchronous Operation ....................................................................................... 346
10.4.4 Buffer Operation.................................................................................................. 348
10.4.5 Cascaded Operation ............................................................................................. 352
10.4.6 PWM Modes........................................................................................................ 354
10.4.7 Phase Counting Mode.......................................................................................... 360
10.5 Interrupts........................................................................................................................... 367
10.5.1 Interrupt Sources and Priorities ........................................................................... 367
10.5.2 DTC Activation ................................................................................................... 369
10.5.3 A/D Converter Activation.................................................................................... 369
10.6 Operation Timing.............................................................................................................. 370
10.6.1 Input/Output Timing............................................................................................ 370
10.6.2 Interrupt Signal Timing ....................................................................................... 374
10.7 Usage Notes ...................................................................................................................... 378
Section 11 Programmable Pulse Generator (PPG) .................................................... 389
11.1 Overview........................................................................................................................... 389
11.1.1 Features................................................................................................................ 389
11.1.2 Block Diagram..................................................................................................... 390
11.1.3 Pin Configuration ................................................................................................ 391
11.1.4 Registers .............................................................................................................. 392
11.2 Register Descriptions........................................................................................................ 393
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 393
11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 394
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 395
11.2.4 Notes on NDR Access ......................................................................................... 395
11.2.5 PPG Output Control Register (PCR) ................................................................... 397
11.2.6 PPG Output Mode Register (PMR) ..................................................................... 399
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 402
11.2.8 Module Stop Control Register A (MSTPCRA) ................................................... 402
Rev. 6.00 Feb 22, 2005 page xliv of lx