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H8S-2639 Datasheet, PDF (161/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer | |||
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Section 4 Exception Handling
4.5 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception
handling.
Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
0
2
Legend:
1: Set to 1
0: Cleared to 0
â: Retains value prior to execution.
CCR
I
UI
1
â
1
â
EXR
I2 to I0
T
â
â
â
0
Rev. 6.00 Feb 22, 2005 page 101 of 1484
REJ09B0103-0600
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