H8S-2639 Datasheet, PDF (1422/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Appendix B Internal I/O Register
TCR3—Timer Control Register 3
H'FE80
TPU3
Bit
Initial value
Read/Write
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
4
3
2
CCLR0 CKEG1 CKEG0 TPSC2
0
0
0
0
R/W R/W R/W R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Time Prescaler
0 0 0 Internal clock: counts on φ/1
1 Internal clock: counts on φ/4
1 0 Internal clock: counts on φ/16
1 Internal clock: counts on φ/64
1 0 0 External clock: counts on TCLKA pin input
1 Internal clock: counts on φ/1024
1 0 Internal clock: counts on φ/256
1 Internal clock: counts on φ/4096
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1  Count at both edges
Counter Clear
Note: Internal clock edge selection is valid when the input clock
is φ/4 or slower. This setting is ignored if the input clock is φ/1,
or when overflow/underflow of another channel is selected.
0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*¹
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input capture*²
1 0 TCNT cleared by TGRD compare match/input capture*²
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*¹
Notes: 1. Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
Rev. 6.00 Feb 22, 2005 page 1362 of 1484
REJ09B0103-0600