H8S-2639 Datasheet, PDF (878/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 21B ROM (H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
21B.7.6 Flash Memory Power Control Register (FLPWCR)
Bit: 7
6
5
4
3
2
1
0
PDWND —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode*.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in
versions other than the U-mask and W-mask versions.
Bit 7—Power-Down Disable (PDWND): The subactive mode is not available in versions other
than the U-mask and W-mask versions.
Only 0 should be written to this bit in the case of versions other than the U-mask and W-mask
versions.
See section 21.B.14, Flash Memory and Power-Down States, for more information.
Bit 7
PDWND
0
1
Description
Transition to flash memory power-down mode enabled
Transition to flash memory power-down mode disabled
(Initial value)
Bits 6 to 0—Reserved: These bits always read 0.
Rev. 6.00 Feb 22, 2005 page 818 of 1484
REJ09B0103-0600