H8S-2639 Datasheet, PDF (126/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 2 CPU
(2) Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES goes high again,
reset exception handling starts. The CPU enters the reset state when the RES is low. When reset
exception handling starts the CPU fetches a start address (vector) from the exception vector table
and starts program execution from that address. All interrupts, including NMI, are disabled during
reset exception handling and after it ends.
(3) Traces
Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR
is set to 1. When trace mode is established, trace exception handling starts at the end of each
instruction.
At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode
is cleared. Interrupt masks are not affected.
The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to
return from the trace exception-handling routine, trace mode is entered again. Trace exception-
handling is not executed at the end of the RTE instruction.
Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.
(4) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer
(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU
alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start
address (vector) from the exception vector table and program execution starts from that start
address.
Figure 2-16 shows the stack after exception handling ends.
Rev. 6.00 Feb 22, 2005 page 66 of 1484
REJ09B0103-0600