H8S-2639 Datasheet, PDF (487/1547 Pages) Renesas Technology Corp – 16-Bit Single-Chip Microcomputer

Section 12 Watchdog Timer
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of reset, see section 4, Exception Handling.
Bit 5
RSTS
0
1
Description
Reset
Do not set
(Initial value)
Bits 4 to 0—Reserved: Always read as 1 and cannot be modified.
12.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
They cannot be written to with byte instructions.
Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
15
Address: H'FF74
H'5A
87
0
Write data
TCSR write
15
Address: H'FF74
H'A5
87
0
Write data
Figure 12-2 Format of Data Written to TCNT and TCSR (WDT0)
Rev. 6.00 Feb 22, 2005 page 427 of 1484
REJ09B0103-0600