HD64F3687GFPV Datasheet, PDF (89/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 3 Exception Handling
3.2.6 Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 overflow interrupts.
Initial
Bit
Bit Name Value R/W Description
7, 6 
All 0

Reserved
These bits are always read as 0.
5
IRRTB1 0
R/W Timer B1 Interrupt Request flag
[Setting condition]
When the timer B1 counter value overflows
[Clearing condition]
When IRRTB1 is cleared by writing 0
4 to 0 
All 1

Reserved
These bits are always read as 1.
3.2.7 Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Initial
Bit
Bit Name Value R/W Description
7, 6 
All 1

Reserved
These bits are always read as 1.
5
IWPF5 0
R/W WKP5 Interrupt Request Flag
[Setting condition]
When WKP5 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0.
4
IWPF4 0
R/W WKP4 Interrupt Request Flag
[Setting condition]
When WKP4 pin is designated for interrupt input and the
designated signal edge is detected.
[Clearing condition]
When IWPF4 is cleared by writing 0.
Rev.5.00 Nov. 02, 2005 Page 55 of 500
REJ09B0027-0500