HD64F3687GFPV Datasheet, PDF (254/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 13 Timer Z
TCNT value
GRA_0
GRB_0
GRA_1
GRB_1
H'0000
FTIOB0
FTIOD0
FTIOA1
FTIOC1
Counter cleared by GRA compare match
Time
FTIOB1
FTIOD1
FTIOC0
Figure 13.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0)
In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent
operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1. When a
compare match occurs between TCNT_0 and GRA_0, a counter is cleared and an increment
operation is restarted from H'0000.
The PWM pin outputs 0 or 1 whenever a compare match between GRB_0, GRA_1, GRB_1 and
TCNT_0 or counter clearing occur.
For details on operations when reset synchronous PWM mode and buffer operation are
simultaneously set, refer to section 13.4.8, Buffer Operation.
Rev.5.00 Nov. 02, 2005 Page 220 of 500
REJ09B0027-0500