HD64F3687GFPV Datasheet, PDF (389/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 EEPROM
SCL
1 2 34 5 6 7891
8 91
891
89
SDA
A15
A8
A7
A0
D7
D0
Slave address
Start
condition
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
R/W ACK
Upper memory
address
ACK
lower memory
address
ACK
Write Data
ACK
Stop
conditon
Figure 19.3 Byte Write Operation
2. Page Write
This LSI is capable of the page write operation which allows any number of bytes up to 8 bytes
to be written in a single write cycle. The write data is input in the same sequence as the byte
write in the order of a start condition, slave address + R/W code, memory address (n), and
write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) is input instead of
receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the
EEPROM address are automatically incremented to be the (n+1) address upon receiving write
data (Dn+1). Thus the write data can be received sequentially.
Addresses in the page are incremented at each receipt of the write data and the write data can
be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last
address of the page, the address will roll over to the first address of the same page. When the
address is rolled over, write data is received twice or more to the same address, however, the
last received data is valid. At the receipt of the stop condition, write data reception is
terminated and the write operation is entered.
The page write operation is shown in figure 19.4.
Rev.5.00 Nov. 02, 2005 Page 355 of 500
REJ09B0027-0500