HD64F3687GFPV Datasheet, PDF (527/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

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13.4.9 Timer Z Output 238
Timing
Figure 13.44 Example of
Output Disable Timing of
Timer Z by Writing to
TOER
φ
Address bus
T1
T2
TOER address
Timer Z
output pin
Timer output
Timer Z output
I/O port
I/O port
Figure 13.45 Example of 238
Output Disable Timing of
Timer Z by External
Trigger
Section 14 Watchdog
252
Timer
14.2.1 Timer
Control/Status Register
WD (TCSRWD)
Section 17 I²C Bus
314
Interface 2 (IIC2)
17.3.5 I²C Bus Status
Register (ICSR)
φ
TOER
N
H'FF
Timer Z
output pin
Timer Z output
Timer Z output
I/O port
I/O port
Bit Bit Name
4 TCSRWE
Description
Timer Control/Status Register WD Write
Enable
Bit Bit Name
3 STOP
Description
Stop Condition Detection Flag
[Setting conditions]
• In master mode, when a stop condition is
detected after frame transfer
• In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with
the address set in SAR
17.7 Usage Notes
336
Section 18 A/D Converter 340
18.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
Added
Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.
Rev.5.00 Nov. 02, 2005 Page 493 of 500
REJ09B0027-0500