HD64F3687GFPV Datasheet, PDF (291/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 15 14-Bit PWM
15.3.2 PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and
PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8
bits to PWDRL. When read, all bits are always read as 1.
Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed
if word access is performed. When 14-bit data is written in PWDRU and PWDRL, the contents
are latched in the PWM waveform generator and the PWM waveform generation data is updated.
When writing the 14-bit data, the order is as follows: PWDRL to PWDRU.
PWDRU and PWDRL are initialized to H'C000.
15.4 Operation
When using the 14-bit PWM, set the registers in this sequence:
1. Set the PWM bit in the port mode register 1 (PMR1) to set the P11/PWM pin to function as a
PWM output pin.
2. Set the PWCR0 bit in PWCR to select a conversion period of either.
3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to
PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these
registers are latched in the PWM waveform generator, and the PWM waveform generation
data is updated in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 15.2. The total high-level width
during this period (T_H) corresponds to the data in PWDRU and PWDRL. This relation can be
expressed as follows:
T_H = (data value in PWDRU and PWDRL + 64) × tφ/2
where tφ is the period of PWM clock input: 2/φ (bit PWCR0 = 0) or 4/φ (bit PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'FFC0 to H'FFFF, the PWM output stays high.
When the data value is H'C000, T_H is calculated as follows:
T_H = 64 × tφ/2 = 32 tφ
Rev.5.00 Nov. 02, 2005 Page 257 of 500
REJ09B0027-0500