HD64F3687GFPV Datasheet, PDF (352/538 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 17 I²C Bus Interface 2 (IIC2)
17.4 Operation
The I²C bus interface can communicate either in I²C bus mode or clocked synchronous serial mode
by setting FS in SAR.
17.4.1 I²C Bus Format
Figure 17.3 shows the I²C bus formats. Figure 17.4 shows the I²C bus timing. The first frame
following a start condition always consists of 8 bits.
(a) I²C bus format (FS = 0)
S
SLA
R/W A
1
7
11
1
DATA
n
A
1
m
A/A P
11
n: Transfer bit count
(n = 1 to 8)
m: Transfer frame count
(m ≥ 1)
(b) I²C bus format (Start condition retransmission, FS = 0)
S
SLA
R/W A
DATA
1
7
11
n1
A/A S
11
SLA
R/W A
7
11
DATA
n2
A/A P
11
1
m1
1
m2
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 ≥ 1)
Figure 17.3 I²C Bus Formats
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
SLA R/W A
DATA
A
DATA
Figure 17.4 I²C Bus Timing
A
P
Legend
S: Start condition. The master device drives SDA from high to low while SCL is high.
SLA: Slave address
Rev.5.00 Nov. 02, 2005 Page 318 of 500
REJ09B0027-0500