H8SX1653 Datasheet, PDF (856/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
In consideration of these conditions, the areas in which the program data can be stored and
executed are determined by the combination of the processing contents, operating mode, and bank
structure of the memory MATs, as shown in tables 20.8 to 20.10.
Table 20.8 Executable Memory MAT
Processing Contents
Programming
Erasing
Operating Mode
User Program Mode
See Table 20.9
See Table 20.10
Table 20.9 Usable Area for Programming in User Program Mode
Storable/Executable Area
Selected MAT
Item
On-Chip RAM User MAT
Embedded
Program
User MAT Storage MAT
Storage area for program data
O
×*


Operation for selecting on-chip
O
program to be downloaded
O
O
Operation for writing H'A5 to FKEY O
O
O
Execution of writing 1 to SCO bit in O
×
O
FCCS (download)
Operation for clearing FKEY
O
O
O
Decision of download result
O
O
O
Operation for download error
O
O
O
Operation for setting initialization
O
parameter
O
O
Execution of initialization
O
×
O
Decision of initialization result
O
O
O
Operation for initialization error
O
O
O
NMI handling routine
O
×
O
Operation for disabling interrupts
O
O
O
Operation for writing H'5A to FKEY O
O
O
Operation for setting programming O
parameter
×
O
Execution of programming
O
×
O
Decision of programming result
O
×
O
Operation for programming error
O
×
O
Operation for clearing FKEY
O
×
O
Note: * Transferring the program data to the on-chip RAM beforehand enables this area to be
used.
Rev.1.00 Sep. 08, 2005 Page 808 of 966
REJ09B0219-0100