H8SX1653 Datasheet, PDF (12/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

5.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions.................... 123
5.8.6 Interrupts of Peripheral Modules .......................................................................... 124
Section 6 Bus Controller (BSC) ........................................................................ 125
6.1 Features.............................................................................................................................. 125
6.2 Register Descriptions......................................................................................................... 128
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 129
6.2.2 Access State Control Register (ASTCR) .............................................................. 130
6.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ......................................... 131
6.2.4 Read Strobe Timing Control Register (RDNCR) ................................................. 136
6.2.5 CS Assertion Period Control Registers (CSACR) ................................................ 137
6.2.6 Idle Control Register (IDLCR) ............................................................................. 140
6.2.7 Bus Control Register 1 (BCR1) ............................................................................ 142
6.2.8 Bus Control Register 2 (BCR2) ............................................................................ 144
6.2.9 Endian Control Register (ENDIANCR) ............................................................... 145
6.2.10 SRAM Mode Control Register (SRAMCR) ......................................................... 146
6.2.11 Burst ROM Interface Control Register (BROMCR) ............................................ 147
6.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 149
6.3 Bus Configuration.............................................................................................................. 150
6.4 Multi-Clock Function and Number of Access Cycles ....................................................... 151
6.5 External Bus....................................................................................................................... 155
6.5.1 Input/Output Pins.................................................................................................. 155
6.5.2 Area Division........................................................................................................ 158
6.5.3 Chip Select Signals ............................................................................................... 159
6.5.4 External Bus Interface .......................................................................................... 160
6.5.5 Area and External Bus Interface ........................................................................... 164
6.5.6 Endian and Data Alignment.................................................................................. 169
6.6 Basic Bus Interface ............................................................................................................ 172
6.6.1 Data Bus ............................................................................................................... 172
6.6.2 I/O Pins Used for Basic Bus Interface .................................................................. 172
6.6.3 Basic Timing......................................................................................................... 173
6.6.4
6.6.5
6.6.6
6.6.7
Wait Control ......................................................................................................... 179
Read Strobe (RD) Timing..................................................................................... 181
Extension of Chip Select (CS) Assertion Period .................................................. 182
DACK Signal Output Timing ............................................................................... 184
6.7 Byte Control SRAM Interface ........................................................................................... 185
6.7.1 Byte Control SRAM Space Setting....................................................................... 185
6.7.2 Data Bus ............................................................................................................... 185
6.7.3 I/O Pins Used for Byte Control SRAM Interface ................................................. 186
6.7.4 Basic Timing......................................................................................................... 187
Rev.1.00 Sep. 08, 2005 Page xii of xlviii