H8SX1653 Datasheet, PDF (37/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Figure 20.10 USB Boot Mode State Transition Diagram ........................................................... 795
Figure 20.11 Programming/Erasing Flow................................................................................... 797
Figure 20.12 RAM Map when Programming/Erasing is Executed ............................................ 798
Figure 20.13 Programming Procedure in User Program Mode .................................................. 799
Figure 20.14 Erasing Procedure in User Program Mode ............................................................ 804
Figure 20.15 Repeating Procedure of Erasing, Programming,
and RAM Emulation in User Program Mode ....................................................... 806
Figure 20.16 Transitions to Error Protection State ..................................................................... 812
Figure 20.17 RAM Emulation Flow ........................................................................................... 813
Figure 20.18 Address Map of Overlaid RAM Area (H8SX/1653) ............................................. 814
Figure 20.19 Programming Tuned Data (H8SX/1653)............................................................... 815
Figure 20.20 Boot Program States .............................................................................................. 817
Figure 20.21 Bit-Rate-Adjustment Sequence ............................................................................. 818
Figure 20.22 Communication Protocol Format .......................................................................... 819
Figure 20.23 New Bit-Rate Selection Sequence......................................................................... 830
Figure 20.24 Programming Sequence......................................................................................... 833
Figure 20.25 Erasure Sequence .................................................................................................. 833
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator ............................................................... 844
Figure 21.2 Connection of Crystal Resonator (Example)........................................................... 848
Figure 21.3 Crystal Resonator Equivalent Circuit ...................................................................... 848
Figure 21.4 External Clock Input (Examples) ............................................................................ 849
Figure 21.5 External Clock Input Timing................................................................................... 849
Figure 21.6 Clock Modification Timing..................................................................................... 851
Figure 21.7 Note on Board Design for Oscillation Circuit ......................................................... 852
Figure 21.8 Recommended External Circuitry for PLL Circuit ................................................. 852
Section 22 Power-Down Modes
Figure 22.1 Mode Transitions..................................................................................................... 855
Figure 22.2 Software Standby Mode Application Example ....................................................... 867
Figure 22.3 Hardware Standby Mode Timing ............................................................................ 868
Figure 22.4 Timing Sequence at Power-On................................................................................ 869
Figure 22.5 When Canceling Factor Interrupt is Generated
after SLEEP Instruction Execution .......................................................................... 872
Figure 22.6 When Canceling Factor Interrupt is Generated
before SLEEP Instruction Execution (Sleep Interrupt Disabled)............................. 872
Figure 22.7 When Canceling Factor Interrupt is Generated
before SLEEP Instruction Execution (Sleep Interrupt Enabled).............................. 873
Rev.1.00 Sep. 08, 2005 Page xxxvii of xlviii