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H8SX1653 Datasheet, PDF (617/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
Section 14 Serial Communication Interface (SCI, IrDA, CRC)
14.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and
it can be read from or written to by the CPU at all times.
Table 14.3 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous
mode
ABCS Bit Bit Rate
0
B=
Pφ × 106
−1
64 × 22n – 1 × B
Error
Pφ × 106
Error (%) = {
– 1 } × 100
B × 64 × 2 2n – 1× (N + 1)
1
B=
Pφ × 106
−1
Error (%) = {
Pφ × 106
– 1 } × 100
32 × 22n – 1 × B
B × 32 × 2 2n – 1× (N + 1)
Clocked synchronous mode
N=
Pφ × 106
−1
8 × 22n – 1 × B
Smart card interface mode
N=
Pφ × 106
−1
S × 22n + 1 × B
Pφ × 106
Error (%) =
{
B × S × 2 2n + 1× (N + 1)
– 1 } × 100
[Legend]
B:
Bit rate (bit/s)
N:
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ:
Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following table.
SMR Setting
SMR Setting
CKS1
CKS0
n
BCP1
BCP0
S
0
0
0
0
0
32
0
1
1
0
1
64
1
0
2
1
0
372
1
1
3
1
1
256
Table 14.4 shows sample N settings in BRR in normal asynchronous mode. Table 14.5 shows the
maximum bit rate settable for each operating frequency. Tables 14.7 and 14.9 show sample N
settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In
smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be
selected. For details, see section 14.7.4, Receive Data Sampling Timing and Reception Margin.
Tables 14.6 and 14.8 show the maximum bit rates with external clock input.
Rev.1.00 Sep. 08, 2005 Page 569 of 966
REJ09B0219-0100