H8SX1653 Datasheet, PDF (574/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 12 8-Bit Timers (TMR)
12.8 Usage Notes
12.8.1 Notes on Setting Cycle
If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in
which the values of TCNT and TCOR match. TCNT updates the counter value at this last state.
Therefore, the counter frequency is obtained by the following formula.
f = φ / (N + 1 )
f: Counter frequency
φ: Operating frequency
N: TCOR value
12.8.2 Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T₂ state of a TCNT write cycle, the clear takes
priority and the write is not performed as shown in figure 12.15.
Pφ
Address
TCNT write cycle by CPU
T₁
T₂
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.15 Conflict between TCNT Write and Clear
Rev.1.00 Sep. 08, 2005 Page 526 of 966
REJ09B0219-0100