H8SX1653 Datasheet, PDF (855/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
• Be sure to initialize both the programming program and erasing program. When the FPEFEQ
parameter is initialized, also initialize both the erasing program and programming program.
Initialization must be executed for both entry addresses: #DLTOP (start address of download
destination for erasing program) + 32 bytes, and #DLTOP (start address of download
destination for programming program) + 32 bytes.
20.7.4 On-Chip Program and Storable Area for Program Data
In the descriptions in this manual, the on-chip programs and program data storage areas are
assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory
which is not to be programmed or erased as long as the following conditions are satisfied.
• The on-chip program is downloaded to and executed in the on-chip RAM specified by
FTDAR. Therefore, this on-chip RAM area is not available for use.
• Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack
area.
• Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip
RAM because it will require switching of the memory MATs.
• In an operating mode in which the external address space is not accessible, such as single-chip
mode, the required procedure programs, NMI handling vector table, and NMI handling routine
should be transferred to the on-chip RAM before programming/erasing starts (download result
is determined).
• The flash memory is not accessible during programming/erasing. Programming/erasing is
executed by the program downloaded to the on-chip RAM. Therefore, the procedure program
that initiates operation, the NMI handling vector table, and the NMI handling routine should be
stored in the on-chip RAM other than the flash memory.
• After programming/erasing starts, access to the flash memory should be inhibited until FKEY
is cleared. The reset input state (period of RES = 0) must be set to at least 100 µs when the
operating mode is changed and the reset start executed on completion of programming/erasing.
Transitions to the reset state are inhibited during programming/erasing. When the reset signal
is input, a reset input state (period of RES = 0) of at least 100 µs is needed before the reset
signal is released.
• When the program data storage area is within the flash memory area, an error will occur even
when the data stored is normal program data. Therefore, the data should be transferred to the
on-chip RAM to place the address that the FMPDR parameter indicates in an area other than
the flash memory.
Rev.1.00 Sep. 08, 2005 Page 807 of 966
REJ09B0219-0100