H8SX1653 Datasheet, PDF (850/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 20 Flash Memory (0.18-µm F-ZTAT Version)
7. Initialization is executed. The initialization program is downloaded together with the
programming program to the on-chip RAM. The entry point of the initialization program is at
the address which is 32 bytes after #DLTOP (start address of the download destination
specified by FTDAR). Call the subroutine to execute initialization by using the following
steps.
MOV.L #DLTOP+32,ER2
; Set entry address to ER2
JSR @ER2
; Call initialization routine
NOP
 The general registers other than ER0 or ER1 are held in the initialization program.
 R0L is a return value of the FPFR parameter.
 Since the stack area is used in the initialization program, a stack area of 128 bytes at the
maximum must be allocated in RAM.
 Interrupts can be accepted during execution of the initialization program. Make sure the
program storage area and stack area in the on-chip RAM and register values are not
overwritten.
8. The return value in the initialization program, the FPFR parameter is determined.
9. All interrupts and the use of a bus master other than the CPU are disabled during
programming/erasing. The specified voltage is applied for the specified time when
programming or erasing. If interrupts occur or the bus mastership is moved to other than the
CPU during programming/erasing, causing a voltage exceeding the specifications to be
applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7
(I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting
bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2.
Accordingly, interrupts other than NMI are held and not executed. Configure the user system
so that NMI interrupts do not occur. The interrupts that are held must be executed after all
programming completes. When the bus mastership is moved to other than the CPU, such as to
the DMAC or DTC, the error protection state is entered. Therefore, make sure the DMAC does
not acquire the bus.
10. FKEY must be set to H'5A and the user MAT must be prepared for programming.
Rev.1.00 Sep. 08, 2005 Page 802 of 966
REJ09B0219-0100