H8SX1653 Datasheet, PDF (525/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.10.10 Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.52 shows the timing in this case.
Pφ
Address
Write
Input capture
signal
TCNT
TGR
Buffer register
Buffer register write cycle
T₁
T₂
Buffer register
address
N
M
N
M
Figure 10.52 Conflict between Buffer Register Write and Input Capture
10.10.11 Conflict between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 10.53 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Rev.1.00 Sep. 08, 2005 Page 477 of 966
REJ09B0219-0100