H8SX1653 Datasheet, PDF (701/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 15 USB Function Module (USB)
15.3.15 EP3 Data Register (EPDR3)
EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data
for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and
setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after
one packet of data has been transmitted successfully, EP3TS in interrupt flag register 0 is set. This
FIFO buffer can be initialized by means of EP3CLR in the FCLR register.
Bit
7
Bit Name
D7
Initial Value Undefined
R/W
W
6
D6
Undefined
W
5
D5
Undefined
W
4
D4
Undefined
W
3
D3
Undefined
W
2
D2
Undefined
W
1
D1
Undefined
W
0
D0
Undefined
W
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value R/W
Undefined W
Description
Data register for endpoint 3 transfer
15.3.16 EP0o Receive Data Size Register (EPSZ0o)
EPSZ0o indicates the number of bytes received at endpoint 0 from the host.
Bit
7
6
5
4
3
2
1
0
Bit Name
—
—
—
—
—
—
—
—
Initial Value
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name
—
Initial
Value
All 0
R/W Description
R
Number of receive data for endpoint 0
Rev.1.00 Sep. 08, 2005 Page 653 of 966
REJ09B0219-0100