H8SX1653 Datasheet, PDF (73/1018 Pages) Renesas Technology Corp – Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

Section 2 CPU
2.3 Instruction Fetch
The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended
that the mode be set according to the bus width of the memory in which a program is stored. The
instruction-fetch mode setting does not affect operation other than instruction fetch such as data
accesses. Whether an instruction is fetched in 16- or 32-bit mode is selected by the FETCHMD bit
in SYSCR. For details, see section 3.2.2, System Control Register (SYSCR).
2.4 Address Space
Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the
CPU operating mode.
Normal mode
H'0000
Middle mode
H'000000
H'FFFF
H'007FFF
Program area
Data area
(64 kbytes)
Advanced mode
H'00000000
Maximum mode
H'00000000
Program area
(16 Mbytes)
Data area
(64 kbytes)
Program area
(16 Mbytes)
H'FF8000
H'FFFFFF
H'00FFFFFF
Program area
Data area
(4 Gbytes)
Data area
(4 Gbytes)
H'FFFFFFFF
Figure 2.8 Memory Map
H'FFFFFFFF
Rev.1.00 Sep. 08, 2005 Page 25 of 966
REJ09B0219-0100