H8S14 Datasheet, PDF (842/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Appendix B Internal I/O Register
TIOR0H—Timer I/O Control Register 0H
H'FF12
TPU0
Bit
:
Initial value :
R/W
:
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
I/O Control A3 to A0
0 0 0 0 TGR0A is
1 output
1 0 compare
1 register
100
1
10
1
1 0 0 0 TGR0A is
1 input capture
1 * register
1**
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input source
isTIOCA0 pin
Setting prohibited
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don’t care
I/O Control B3 to B0
0 0 0 0 TGR0B is
1 output
1 0 compare
1 register
100
1
10
1
1 0 0 0 TGR0B is
1 input capture
1 * register
1**
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input source
isTIOCB0 pin
Setting prohibited
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
*: Don’t care
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
Rev.4.00 Sep. 18, 2008 Page 780 of 872
REJ09B0189-0400