H8S14 Datasheet, PDF (478/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.5 Interrupts
10.5.1 Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 10.12 lists interrupt sources and DMA controller (DMAC) and data transfer controller
(DTC) activation.
Table 10.12 Interrupt Sources and DMA Controller (DMAC) and Data Transfer (DTC)
Activation
Interrupt
Channel Source Description
DMAC
Activation
DTC
Activation Priority
0
TGI0A
TGR0A input capture/compare match Possible
Possible
High
TGI0B
TGR0B input capture/compare match Not possible Possible
TGI0C
TGR0C input capture/compare match Not possible Possible
TGI0D
TGR0D input capture/compare match Not possible Possible
TCI0V
TCNT0 overflow
Not possible Not possible
1
TGI1A
TGR1A input capture/compare match Possible
Possible
TGI1B
TGR1B input capture/compare match Not possible Possible
TCI1V
TCNT1 overflow
Not possible Not possible
TCI1U
TCNT1 underflow
Not possible Not possible
2
TGI2A
TGR2A input capture/compare match Possible
Possible
TGI2B
TGR2B input capture/compare match Not possible Possible
TCI2V
TCNT2 overflow
Not possible Not possible
TCI2U
TCNT2 underflow
Not possible Not possible Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
Rev.4.00 Sep. 18, 2008 Page 416 of 872
REJ09B0189-0400