H8S14 Datasheet, PDF (495/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
(9) Contention between TGR Write and Input Capture
If the input capture signal is generated in the T₂ state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T₁
T₂
TGR address
M
TGR
M
Figure 10.50 Contention between TGR Write and Input Capture
Rev.4.00 Sep. 18, 2008 Page 433 of 872
REJ09B0189-0400