H8S14 Datasheet, PDF (380/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 9 I/O Ports
(4) Port A MOS Pull-Up Control Register (PAPCR)
Bit
:7
6
5
4
3
2
1
0
—
—
—
— PA3PCR PA2PCR PA1PCR PA0PCR
Initial value : Undefined Undefined Undefined Undefined 0
0
0
0
R/W
:—
—
—
—
R/W
R/W
R/W
R/W
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on a bit-by-bit basis.
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PAPCR is valid for port input and SCI input pins. When a PADDR bit is cleared to 0 (input port
setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the
corresponding pin.
PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
(5) Port A Open-Drain Control Register (PAODR)
Bit
:7
6
5
4
3
2
1
0
—
—
—
— PA3ODR PA2ODR PA1ODR PA0ODR
Initial value : Undefined Undefined Undefined Undefined 0
0
0
0
R/W
:—
—
—
—
R/W
R/W
R/W
R/W
PAODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port A
pin (PA3 to PA0).
Bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read.
PAODR is valid for port output and SCI output pins.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output pin,
while clearing the bit to 0 makes the pin a CMOS output pin.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its previous state after a manual reset and in software standby mode.
Rev.4.00 Sep. 18, 2008 Page 318 of 872
REJ09B0189-0400