H8S14 Datasheet, PDF (649/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

A18 to A0
CE
Command write
t_ces
t_ceh
t_nxtc
Section 15 ROM
Memory read mode
Address stable
OE
WE
I/O7 to I/O0
t_wep
t_f
t_r
t_ds
t_dh
Note: Data is latched on the rising edge of WE.
Figure 15.21 Timing Waveforms for Memory Read after Memory Write
Table 15.16 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: V_CC = 3.3 V ±0.3 V, V_SS = 0 V, T_a = 25°C ±5°C
Item
Command write cycle
CE hold time
CE setup time
Data hold time
Data setup time
Write pulse width
WE rise time
WE fall time
Symbol
t_nxtc
t_ceh
t_ces
t
dh
t_ds
t_wep
t_r
t_f
Min.
20
0
0
50
50
70
Max.
Unit
µs
ns
ns
ns
ns
ns
30
ns
30
ns
Notes
Rev.4.00 Sep. 18, 2008 Page 587 of 872
REJ09B0189-0400