H8S14 Datasheet, PDF (327/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Section 8 Data Transfer Controller (DTC)
Source flag cleared
Clear
DTCER
Select
Clear
controller
Clear request
On-chip
supporting
module
IRQ interrupt
DTVECR
Interrupt
request
DTC
Interrupt controller
Interrupt mask
CPU
Figure 8.3 Block Diagram of DTC Activation Source Control
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
8.3.3 DTC Vector Table
Figure 8.4 shows the correspondence between DTC vector addresses and register information.
Table 8.4 shows the correspondence between activation and vector addresses. When the DTC is
activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where
<< 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
The DTC reads the start address of the register information from the vector address set for each
activation source, and then reads the register information from that start address. The register
information can be placed at predetermined addresses in the on-chip RAM. The start address of
the register information should be an integral multiple of four.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip
RAM.
Note: * Not available in the H8S/2214 Group.
Rev.4.00 Sep. 18, 2008 Page 265 of 872
REJ09B0189-0400