H8S14 Datasheet, PDF (840/938 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2200 Series

Appendix B Internal I/O Register
TCR0—Timer Control Register 0
H'FF10
TPU0
Bit
:
Initial value :
R/W
:
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Time Prescaler 2 to 0
000
1
10
1
100
1
10
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
Clock Edge 1 and 0
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
Counter Clear 2 to 0
000
1
10
1
100
1
10
1
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel performing
synchronous clearing/synchronous operation ^*1
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture ^*2
TCNT cleared by TGRD compare match/input capture ^*2
TCNT cleared by counter clearing for another channel performing
synchronous clearing/synchronous operation ^*1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit
in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and compare
match/input capture does not occur.
Rev.4.00 Sep. 18, 2008 Page 778 of 872
REJ09B0189-0400