HB28K032MM3 Datasheet, PDF (83/91 Pages) Renesas Technology Corp – MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

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t_PP
t_WH
t_WL
V_IH
Clock
Input
t_IH
Valid data
t_HL
t_LH
Valid data
t_ISU
V_IL
V_IH
V_IL
V_OH
Output
t_OH
Valid data
t_OSU
V_OL
: Invalid
Timing Diagram of Data Input and Output
The access time (t_AT) is divided into two parts:
• T_SAD: The synchronous access time. This time defines the time of the maximum number of cycles
which are required to access a byte of the memory field.
• T_AAD: The asynchronous access time to read a byte out of the memory field.
The synchronous part of the access time is sum of the command frame length and some additional internal
cycles (N_SAD = 16 cycles). At 20 MHz one cycle is 50 ns (1/f_PP), multiplied with N_SAD the resulting frame
time is T_SAD = 0.8 µs. The asynchronous access delay of these Renesas MultiMediaCards is T_AAD = 300 µs
typical. The resulting memory access time t_AT is the sum of both parts:
t_AT = T_AAD + T_SAD
with
T_SAD = N_SAD / f_PP
CMD
command frame
T_SAD
t_AT
T_AAD
response frame
DAT
data
Access Time
Rev.0.02, Sep.15.2004, page 83 of 89