HB28K032MM3 Datasheet, PDF (70/91 Pages) Renesas Technology Corp – MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
SPI Bus Timing
All timing diagrams use the following schematics and abbreviations:
H: Signal is high (logical ‘1’)
L: Signal is low (logical ‘0’)
X: Don’t care
Z: High impedance state (-> = 1)
*: Repeater
Busy: Busy token
Command: Command token
Response: Response token
Data block: Data token
All timing values are defined in Table “Timing Values”. The host must keep the clock running for at least
N_CR clock cycles after receiving the card response. This restriction applies to both command and data
response tokens.
Command/Response
• Host Command to Card Response - Card is ready
CS
Datain
HHL L L
N_CS
XXH H HH
******************
6 bytes command H H H H H
*******
Dataout Z Z Z H H H H * * * * * * *
N_CR
HHHH H
1 or 2 bytes response
L L L L HHH
N_EC
H HH HXX X
H HH HHZ Z
• Host Command to Card Response - Card is busy
CS H L L L
******************
L LL L HHH L LL L L L HH
N_CS
N_EC
N_DS
N_EC
Datain X H H H H 6 bytes command H H H H H H H H H H H H H X X X H H H H H H X X
N_CR
Dataout Z Z H H H H * * * * * * * H H H H _{card response busy} L Z Z Z busy H H H H Z
Rev.0.02, Sep.15.2004, page 70 of 89