HB28K032MM3 Datasheet, PDF (48/91 Pages) Renesas Technology Corp – MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S: Start bit (= 0)
T: Transmitter bit (Host = 1, Card = 0)
P: One-cycle pull-up (= 1)
E: End bit (= 1)
Z: High impedance state (-> = 1)
D: Data bits
*: Repeater
CRC: Cyclic redundancy check bits (7 bits for command or response, 16 bits for block data)
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up
resistors R_CMD respectively R_DAT. Actively driven P-bits are less sensitive to noise superposition. For the
timing of these Renesas MultiMediaCards, the following values are defined:
Timing Values
Value [clock cycles]
Symbol
Min
Max
Description
N_CR
2
64
Number of cycles between command and
response
N
5
5
Number of cycles between card identification
ID
or card operation conditions command and the
corresponding response
N_AC
2*¹
TAAC + NSAC*² Number of cycles between a command and the
start of a related data block
N
RC
8

Number of cycles between the last response
and a new command
N_CC
8

Number of cycles between two commands, if
no response will be sent after the first
command (e.g. broadcast)
N_WR
2

Number of cycles between a write command
and the start of a related data block
N_ST
2
2
Number of cycles between stop command and
valid read / write data end
Notes: 1. Refer to Chapter “Electrical Characteristics” for more details about the access time.
2. Refer to Chapter “Read, Write and Erase Time-out Conditions”.
Rev.0.02, Sep.15.2004, page 48 of 89