HB28K032MM3 Datasheet, PDF (52/91 Pages) Renesas Technology Corp – MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
• Stream write
The data transfer starts N_WR clock cycles after the card response to the sequential write command was
received. The bus transaction is identical to that of a write block command (see Figure “Timing of The
Block Write Command”). As the data transfer is not block-oriented, the data stream does not include the
CRC checksum. Consequently the host can not receive any CRC status information from the card. The
data stream is terminated by a stop command. The bus transaction is identical to the write block option
when a data block is interrupted by the stop command (see Figure “Stop Transmission During Data
Transfer From The Host”).
Host command
N_CR cycles
Card response
CMD S T content CRC E Z Z P * * * P S T content CRC E
N_ST
Card is programming
DAT D D D D D D D D D D E Z Z S L * * * * * * * * * * * * * * * * * *
Valid write data
Host command
S T content
EZZZZZZZZ
Stop Transmission During Data Transfer From The Host
• Erase block timing
The host must first tag the group to erase. The tagged group(s) are erased in parallel by using the CMD35,
CMD36 and CMD38. The card busy signaling is also used for the indication of the card erase procedure
duration. In this case the end of the card busy signaling also does mean that the erase of all tagged groups
has been finished. The host can (also) request the card to send the actual card state using the CMD13.
CMD
DAT
CMD
N_CR
Card response
T content CRC E
S T content CRC E
Host active
card is erasing
card busy
Z Z *********** Z Z Z S L L ******************** L E
Host command
Card active
S T content CRC E
Host active
DAT _{L * * * * * L E Z * * * * * * * *}
Card active
L ... pull down to LOW bit
Timing of Erase Operation
Rev.0.02, Sep.15.2004, page 52 of 89