HB28K032MM3 Datasheet, PDF (72/91 Pages) Renesas Technology Corp – MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
• Reading The CSD Register
CS H L L L
******************
L L L H H HH
N_CS
N_EC
Datain X H H H H read command H H H H H
*******
H HH X X XX
N_CR
N_CX
Dataout Z Z H H H H * * * * * * * H H H H _{card response} H H H H data block H H H H Z Z Z
• Single Block Write
CS _{H L}
******************
L L L L L L L L HHHL L L L
Datain
N_CS
N_WR
X H ** H Write command H H H H H H H H ** H Data block H H
N_EC
N_DS
H H ** H X ** X H H H H
Dataout
Z Z H H H *******
N_CR
H ** H
Card
response
HHHHHHH
Data
resp
Busy L Z Z Z Busy H
• Multiple Block Write
CS
Datain
Dataout
L
******************
L L L L LLL L L L L L L L L L L L L L
N_WR
N_WR
H Data Block H H H H H H H H * * H ^{Data Block} H H H H H H H H * * H Stop Tran H H H H H
N_BR
H H H H H Data Resp Busy H H H H H H H Data Resp Busy H H H H H H X * * X Busy
Timing Values
Symbol
Min
Max
N_CS
N
CR
N
CX
N
RC
N_AC
N_WR
N_EC
N_DS
N_BR
Note:
0

1
8
0
8
1

1
spec. in the CSD*¹
1

0

0

1
1
1. Refer to Chapter “Read, Write and Erase Time-out Conditions”.
Unit
8 clock cycles
8 clock cycles
8 clock cycles
8 clock cycles
8 clock cycles
8 clock cycles
8 clock cycles
8 clock cycles
8 clock cycles
Rev.0.02, Sep.15.2004, page 72 of 89