HB28K032MM3 Datasheet, PDF (37/91 Pages) Renesas Technology Corp – MultiMediaCard 32 MByte/64 MByte/128 MByte/256 MByte/512 MByte

HB28K032/L064/J128/J256/J512MM3, HB28K032/L064/J128/J256RM3
If the card detects an error (e.g. out of range, address misalignment, internal error, etc.) during a multiple
block read operation (both types) it will stop data transmission and remain in the Data State. The host must
than abort the operation by sending the stop transmission command. The read error is reported in the
response to the stop transmission command.
If the host sends a stop transmission command after the card transmits the last block of a multiple block
operation with a pre-defined number of blocks, it will be responded to as an illegal command, since the
card is no longer in data state.
If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not
allowed, the card shall detect a block misalignment error condition at the beginning of the first misaligned
block (ADDRESS_ERROR error bit will be set in the status register).
• Stream write
Stream write (CMD20) starts the data transfer from the host to the card beginning from the starting address
until the host issues a stop command. If partial blocks are allowed (if CSD parameter
WRITE_BL_PARTIAL is set) the data stream can start and stop at any address within the card address
space, otherwise it shall start and stop only at block boundaries. Since the amount of data to be transferred
is not determined in advance, CRC can not be used. If the end of the memory range is reached while
sending data and no stop command has been sent by the host, all further transferred data is discarded. The
maximum clock frequency for stream write operation is given by the following formula:
max. speed = min (TRAN_SPEED, (8 * 2^WRITE_BL_LEN − NSAC) / (TAAC * R2W_FACTOR))
= min (20, (8 * 2⁹ − 100 [cycles]) / 1000 [µs] * 4)[MHz] = min (20, 0.999) = 0.999 [MHz]
these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the
card may not be able to process the data and will stop programming, set the OVERRUN error bit in the
status register, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop
command. The write operation shall also be aborted if the host tries to write over a write-protected area.
In this case, however, the card shall set the WP_VIOLATION bit.
• Block write
Block write (CMD24 − 27) means that one or more blocks of data are transferred from the host to the card
with a 16-bit CRC appended to the end of each block by the host. A card supporting block write must
always be able to accept a block of data defined by WRITE_BLK_LEN. If the CRC fails, the card will
indicate the failure on the DAT line; the transferred data will be discarded and not written and all further
transmitted blocks (in multiple block write mode) will be ignored.
WRITE_MULTIPLE_BLOCK (CMD25) starts a transfer of several consecutive blocks. Two types of
multiple block write transactions, identical to the multiple block read, are defined (the host can use either
one at any time):
• Open-ended Multiple block write
The number of blocks for the write multiple block operation is not defined. The card will
continuously accept and program data blocks until a stop transmission command is received.
Rev.0.02, Sep.15.2004, page 37 of 89