HD6473228P10V Datasheet, PDF (77/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Bit i (i = 0 to 2)
IRQiE
0
1
Description
IRQi is disabled.
IRQi is enabled.
(Initial state)
Edge-sensed interrupt signals are latched (if enabled) and held until the interrupt is served. They are
latched even if the interrupt mask bit (I) is set in the CCR, and even if bits IRQ0E to IRQ2E are
cleared to 0. Level-sensed interrupts are not latched.
4.3.3 External Interrupts
The external interrupts are NMI and IRQ0 to IRQ2.
While the CPU is waiting for one of these interrupts, it is possible to conserve power by entering
software standby mode. When the interrupt arrives, the chip will recover automatically to the
program execution state, handle the interrupt, then continue executing the main program. See
section 12, Power-Down State for further information on software standby mode.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected
by the NMIEG bit in the system control register.
An NMI has highest priority and is always accepted as soon as the current instruction ends, unless
the current instruction is an ANDC, ORC, XORC, or LDC instruction. When an NMI interrupt is
accepted the interrupt mask (I bit) is set, so the NMI handling routine cannot be interrupted except
by another NMI.
The NMI vector number is 3. Its entry is located at address H’0006 in the vector table.
(2) IRQ0 to IRQ2: These interrupt signals are level-sensed or sensed on the rising or falling edge
of the input, as selected by the ISCR bits. These interrupts can be masked collectively by the I bit in
the CCR, and can be enabled and disabled individually by setting and clearing the bits in the IRQ
enable register. When one of these interrupts is accepted, the I bit is set to 1 to mask further
interrupts (except NMI).
These interrupts are second in priority to NMI. Among them, IRQ0 has the highest priority and
IRQ2 the lowest priority. Interrupts IRQ0 to IRQ2 do not depend on whether pins IRQ0 to IRQ2 are
input or output pins. When using external interrupts IRQ0 to IRQ2, clear the corresponding DDR
bits to 0 to set these pins to the input state.
68