HD6473228P10V Datasheet, PDF (172/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

(2) Contention between TCNT Write and Increment: If a timer counter increment pulse is
generated during the T3 state of a write cycle to the timer counter, the write takes priority and the
timer counter is not incremented.
Figure 8-14 shows this type of contention.
Write cycle: CPU writes to TCNT
T1
T2
T3
Ø
Internal Address
bus
Internal write
signal
TCNT clock
pulse
TCNT address
TCNT
N
M
Write data
Figure 8-14. TCNT Write-Increment Contention
(3) Contention between TCOR Write and Compare-Match^F:^iguI^rf^ea⁷c^-1o⁴mpare-match occurs during
the T3 state of a write cycle to TCORA or TCORB, the write takes precedence and the compare-
match signal is inhibited.
Figure 8-15 shows this type of contention.
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