HD6473228P10V Datasheet, PDF (168/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Figure 8-7 shows the timing when the output is set to toggle on compare-match A.
Ø
Internal
compare-match
A signal
Timer output
(TMO)
Figure 8-7. Timing of Timer Output
(4) Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in the TCR,
the timer counter can be cleared when compare-match A or B occurs. Figure 8-8 shows the timing
of this operation.
Øø
Internal
compare-match
signal
TCNT
N
H’00
Figure 8-8. Timing of Compare-Match Clear
8.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in the TCR are both set to 1, the timer counter is cleared on the
rising edge of an external reset input. Figure 8-9 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock periods.
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