HD6473228P10V Datasheet, PDF (223/301 Pages) Renesas Technology Corp – Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp

Section 12. Power-Down State
12.1 Overview
The H8/325 series has a power-down state that greatly reduces power consumption by stopping
some or all of the chip functions. The power-down state includes three modes:
(1) Sleep mode – a software-triggered mode in which the CPU halts but the rest of the chip
remains active
(2) Software standby mode – a software-triggered mode in which the entire chip is inactive
(3) Hardware standby mode – a hardware-triggered mode in which the entire chip is inactive
Table 12-1 lists the conditions for entering and leaving the power-down modes. It also indicates the
status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 12-1. Power-Down State
Mode
Sleep
mode
Soft-
ware
standby
mode
Hard-
ware
standby
mode
Entering
procedure
Clock
Execute
Run
SLEEP
instruction
Set SSBY bit Halt
in SYSCR to
1, then
execute SLEEP
instruction
Set STBY
Halt
pin to low
level
CPU
Halt
Halt
Halt
CPU Sup.
Reg’s. Mod.* RAM
Held Run Held
Held Halt Held
and
initial-
ized
Not Halt Held
held and
initialized
I/O
ports
Held
Held
High
impe-
dance
state
Exiting
methods
• Interrupt
• RES
• STBY
• NMI
• IRQ0 – IRQ2
• STBY
• RES
• IS
• STBY high,
then RES
low → high
* On-chip supporting modules.
Notes
1. SYSCR: System control register
2. SSBY: Software standby bit
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